Reliable interconnection of semiconductor integrated circuit chips and supporting substrates depends on avoiding stresses, including thermal expansion stresses, that can crack interconnects. Usually integrated circuits are mounted on supporting substrates made of material with a coefficient of thermal expansion that differs from the coefficient of thermal expansion of the material of the integrated circuit. For example, the integrated circuit may be formed of monocrystalline silicon with a coefficient of thermal expansion of 2.5.times.10.sup.-6 per .degree. C. and the supporting substrate may be formed of a ceramic material, such as alumina, with a coefficient of thermal expansion of 5.8.times.10.sup.-6 per .degree. C. In operation, the integrated circuit chip generates heat which raises the temperature of both the chip and the supporting substrate. Because of different temperatures and different coefficients of thermal expansion, the chip and substrate expand and contract different amounts. This difference in expansion imposes stresses on connections, such as the relatively rigid C4 solder bumps that are frequently used to provide an area array interconnection between a chip and a substrate. The stress on the solder bumps is directly proportional to (1) the magnitude of the temperature difference, (2) the distance of an individual bump from the neutral or central point of the solder bump array, and (3) the difference in the coefficients of thermal expansion of the material of the semiconductor device and the substrate, and inversely proportional to the height of the solder bond, that is the spacing between the IC chip and the support substrate.
Several factors are currently compounding the problem. As the solder bumps become smaller in diameter in order to accommodate the need for a greater density of interconnects between chip and substrate, the overall height of each solder bump decreases, reducing the fatigue life of the solder bumps. In addition, integrated circuit chip sizes are increasing which increases the distance of the outer solder bumps from the neutral point of the solder bump array, which in turn reduces the fatigue life of the solder bump. Furthermore, chips are now being directly mounted on substrates, such as PC boards, that have substantially larger coefficients of thermal expansion than ceramic, adding substantially to the stress on connectors. Thus, a better solution is needed that provides a way to reduce thermal stress and to provide a more reliable electrical connection, and this solution is provided by the following invention.